The present invention relates to apparatus and methods for chemical mechanical polishing a substrate.
An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulative layers on a silicon wafer. One fabrication step involves depositing a filler layer over a patterned stop layer, and planarizing the filler layer until the stop layer is exposed. For example, trenches or holes in an insulative layer may be filled with a conductive layer. After planarization, the portions of the conductive layer remaining between the raised pattern of the insulative layer form vias, plugs and lines that provide conductive paths between thin film circuits on the substrate.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a rotating polishing pad. The polishing pad may be either a standard pad or a fixed-abrasive pad. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. The carrier head provides a controllable load, i.e., pressure, on the substrate to push it against the polishing pad. A polishing slurry, including at least one chemically-reactive agent, and abrasive particles if a standard pad is used, is supplied to the surface of the polishing pad.
An effective CMP process not only provides a high polishing rate, but also provides a substrate surface which is finished (lacks small-scale roughness) and flat (lacks large-scale topography). The polishing rate, finish and flatness are determined by the pad and slurry combination, the relative speed between the substrate and pad, and the force pressing the substrate against the pad. The polishing rate sets the time needed to polish a layer, which in turn sets the maximum throughput of the CMP apparatus.